NAND flash memory is well known as one type of non-volatile semiconductor device that can be rewritten electronically. To improve bit density of NAND flash memories, because the miniaturization technology is reaching its limit, lamination of memory cells are being expected.
When erasing data in the conventional flat panel NAND flash memory, a voltage of about 0V is provided to the gate of the memory cell, and an erasing voltage of high voltage is provided to the well where the memory cells are formed. In the case when one erase operation does not decrease the memory cell threshold to a desired value, another erase operation is performed. During this time, the erasing voltage is set to a higher value than the value used in the previous erase operation.
In a laminated (stacked or layered) NAND flash memory, the types of voltages used when erasing data, as compared to the conventional flat panel NAND flash memory, have increased. However, a method to step up the various voltages used when erasing data, as well as a memory device adapted for this method, has not been established.